Srivastava, Viranjay Mohan.Maduagwu, Uchechukwu Anthony.2026-01-212026-01-2120242024https://hdl.handle.net/10413/24238Doctoral Degree. University of KwaZulu-Natal, Durban.The advancement of Very Large-Scale Integration (VLSI) and nanotechnology systems has been significantly driven by the miniaturization of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) devices. Moore’s Law substantiates this trend, affirming that ”the quantity of transistors integrated into a semiconductor device or chip approximately doubles every two years.” The principal objectives of transistor scaling are to enhance functionality, packing density, switching speed, and operational power of integrated circuits (ICs). With the technological advancement below the 100 nm regime, conventional MOSFETs appear to be of little use for scaling because of Short Channel Effects(SCEs). These SCEs encompass threshold roll-off, Drain-Induced Barrier Lowering (DIBL), surface scattering, velocity saturation, mobility degradation, and the hot carrier effect. Other effects include oxide gate tunneling and process variation. These effects contribute to the deterioration of device performance. Consequently, unconventional devices are essential to meet the goals of the International Technology Roadmap for Semiconductors (ITRS). These non-conventional devices, such as Silicon- On-Insulator (SOI) substrate gates, double gates, triple gates, surrounding gates, and double surrounding gates, uphold Moore’s law. Among these unconventional MOSFETs, the double surrounding gates’ solution has a promising future. The only MOSFET category under the double surrounding gate is known as the Cylindrical Surrounding Double Gate (CSDG) MOSFETs, which was proposed a few years ago. The CSDG is a MOSFET device structure with a hollow cylindrical structure. In relation to the source, drain, gate, and channel, it exhibits similarities with both traditional MOSFETs and non-conventional Cylindrical Surrounding Gate (CSG) MOSFETs. However, the channel, on the other hand, is controlled by both the internal and external gates. The primary function of the two gates is to provide electrical shielding against the lateral electric field generated by the charges in the drain and source regions. Furthermore, numerous research studies have been undertaken utilizing this device architecture. The natural length varies from different MOSFET structures to the other, and It aids in characterizing the potential distribution within the Silicon substrate. In this thesis, the authors proposed a natural length scaling pattern for measuring the degree of SCEs of CSDG MOSFETs, which will guide the device design. This was done by solving the Poisson equation of the cylindrical structure using the Parabolic Potential Approximation (PPA) model at the radial part of the device structure. The natural length was derived and compared with other device geometrical structures and validated with numerical structure. Moreover, the determined intrinsic length was employed to anticipate the threshold voltage response of the device configuration. In addition, a quantum scaling length for CSDG MOSFET was developed within the Silicon body thickness to investigate the degree of fluctuation of the device structure and to provide design guidelines for the device structure. The authors conducted the analysis using a unified quantum model that considered the lowest electron energy level as the reference point. The relationship between the quantum scaling length and natural scaling length of CSDG MOSFET was proposed. Also, the space confinement known as the quantum scaling factor was analyzed based on the variation in threshold voltage. The results obtained are in good agreement with numerical simulation. Furthermore, the solution to the Poisson equation is investigated, and the Silicon-oxide is replaced with high-k dielectric to analyze the CSDG MOSFET’s sensitivity to process variation for both lightly and heavily doped device structure. The device’s immunity to channel variation was analyzed. Also, Random Dopant Fluctuations (RDFs), which severely affect non-conventional devices, was investigated. The model is juxtaposed with CSG structure, and the assessment of the threshold voltage’s susceptibility to parameter variations is further scrutinized with a focus on RDFs. The results obtained demonstrated excellent consistency with numerical simulations. Ultimately, the analytical approach employed for deducing the natural length of CSDG MOSFET is extended to apply to the surface potential, allowing for the modeling of a triple-gate material variant of CSDG MOSFET with hetero-dielectric oxide. In this model, the concepts of metal gate engineering and oxide engineering have been integrated with CSDG MOSFET to suppress SCEs further. The newly proposed Stacked Triple Material Gate (STMG) CSDG MOSFET adjusts the performance matrices of the CSDG MOSFET to provide better performance at the deep sub-22 nm technology node. A 2- D analytical model for STMG CSDG MOSFET has been formulated and introduced. This model is established by solving the 2-D Poisson equation with the utilization of the PPA approach. The developed surface potential is utilized in the development of the threshold voltage model for STMG CSDG MOSFETs and the derivation of DIBL. The model was then used to estimate the subthreshold drain current and further enhance the subthreshold swing. The results show that STMG CSDG MOSFET improves the SCEs characteristics. The numerical simulation is in accordance with the analytical model.enCC0 1.0 Universalhttp://creativecommons.org/publicdomain/zero/1.0/Very Large-Scale Integration (VLSI).Metal-Oxide-Semiconductor Field Effect Transistors.Moore’s Law.Short Channel Effects (SCEs).Thesis