The Design of high-voltage planar transistors with specific reference to the collector region.
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Date
1984
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Abstract
The thesis represents a major contribution to the understanding of
the design and fabrication of high-voltage planar silicon bipolar transistors,
and reports on the original research carried out and the special
methods evolved leading to the successful design, development and industrialization
of two highly specialized transistors. The development of
these transistors, destined for high-reliability applications in subscriber
telephone systems, was funded by the South African Department of Posts
and Telecommunications.
The first device developed was a discrete transistor meeting the
requirements of a singularly difficult specification that included the
following.
An accurately controlled upper limit to quasi-saturation operation,
so that above a collector-emitter voltage of 4 V at 60 mA,
the device characteristics should be extremely linear.
An extremely small range of acceptable gains, with lower and
upper limits of 80 and 180 respectively.
Both accurately reproducible and high breakdown-voltages
exceeding 200 V.
The ability to withstand 100 W pulses of 10ps duration at a case
temperature of 95 °c and a collector-emitter voltage of 130 V.
The second device represents a design and development breakthrough
resulting in a unique high-voltage integrated Darlington transistor incorporating
the following design features.
The standard discrete high-voltage transistors used initially in
the Darlington application were found to fail frequently due to
an external breakdown mechanism under lightning surge conditions,
which are common in South Africa. To overcome this weakness, the
integrated Darlington incorporates a special clamping circuit to
absorb the surge energy non-destructively within the bulk of the
device and thereby prevent external breakdown.
To act as an electrostatic shielding system a new 'inverted
metallization structure' was developed and incorporated in
the Darlington transistor design. With this structure it was
possible to realize transistors with a combination of extremely
high gains, approaching 105 , and very low collector-emitter
leakage currents, often lower than 1 nA at an applied 240 V,
and no device with comparable properties has been reported on
elsewhere.
During the development of the integrated Darlington it was recognized
that there was a necessity for a simple yet accurate method of predicting
quasi-saturation operation. This consideration led to the development of
a totally new, user-orientated, graphical model for predicting the gain of
a transistor when operating in the quasi-saturation mode a model involving
the use of entirely new yet easily measured parameters. The model was
successfully applied to the verification of the Darlington design and the
optimization of processing parameters for the device.
Although undertaken in a research environment, the projects were
handled under pressures normally associated with industrial conditions.
Time schedules were constrained, and this influenced design strategy. As
a consequence, however, the need arose to develop fast and efficient design
aids since much of the theoretical design was implemented for production
without recourse to long-term experimental verification in the laboratory.
Whilst the author viewed this approach as less than ideal, the successful
production of almost two million of these highly specialized devices, including
both types, has lent authority to the design techniques developed.
In spite of the industry-like pressures imposed during the course of
the work, many aspects of the development programmes were further investigated
and refined by research that would have been omitted had the author accepted
the realization of a working device as the only goal. This research has not
only contributed to the production of devices of exceptionally high quality,
but has also produced a wealth of new information valuable to future designers.
These aids include a new and highly accurate correction for the parasitic
collector resistance of a transistor; design data for the specification of
epitaxial layers for transistors with collector-emitter breakdown voltages
ranging between 5 V and 800 V; information on Gate Associated Transistor
(GAT) structures; and the entirely new graphical method, mentioned above,
for modelling saturation effects in bipolar transistors.
Process development was successfully carried out within the strict
confines of compatibility with available equipment, and the pre-requisite that
the existing production of low-voltage bipolar integrated circuits should in
no way be compromised. Successful transfer of the technology, followed by
industrialization, has demonstrated the effectiveness of a method developed
by the author for the rapid communication and dissemination of appropriate
information in a system without precedents for such procedures.
Listed below are other examples showing that useful information was
gathered and new techniques developed.
Emitter-region defects associated with the metallization
process were identified.
Test data were used to monitor project performance and in
the development of data management techniques.
Interaction with the author resulted in the establishment
of the first Quality Assurance and Audit function for microelectronics
activities by the Department of Posts and Telecommunications
in the Republic of South Africa. The group
formed had the authority to handle the certification of semiconductor
capabilities and the qualification for service of
semiconductor components.
An entirely new continuous failure analysis programme was introduced
covering both the products manufactured and similar types
from other sources: a programme that has brought to light the
major failure mechanisms in the high-voltage transistors.
On the basis of the knowledge gained during the research and development
programmes it has been possible to make recommendations, substantiated
by preliminary investigations for further original research work on a new type
of negative-resistance high-voltage device. This would initially be destined
for use in subscriber telephones to improve their immunity to surges, and it
would form the basis of the development of a totally new type of interface
circuit with in-built protection against surges, for application at the subscriber
line interface in electronic exchanges.
Description
Thesis (Ph.D.) - University of Natal, Durban, 1984.
Keywords
Planar transistors--Design., Theses--Electronic engineering.