Implementation of a WCDMA AAA receiver on an FPGA based software radio platform.
WCDMA promises to achieve high-speed internet, high quality image transmission and high-speed data services with larger system capacity. However, Multiple Access Interference is one of the major causes of transmission impairment, which reduces the link capacity in WCDMA systems. The Adaptive Antenna Array (AAA) technique reduces multiple access interference by directing antenna beam nulls towards the interfering signals by weighting the received signals from all antennas before combining the signals. With the very rapid advancement of wireless personal communications services, a new challenge to the cellular industry is the integration of multiple systems and applications on a single device. A software radio technique offers a possible solution to achieve this goal including international roaming and multiple standard operations within the same geographical area. The main attraction of a software radio is it's flexibility, in that it can be programmed for emerging cellular standards allowing it to be updated with new software without any changes in the hardware infrastructure. A software radio incorporating adaptive array beamforming at the receiver can increase the total carried traffic in a system and transmit power while the probability of call blocking and forced termination can also be decreased. This dissertation examines WCDMA, AAA, power control and software radio techniques in the world of wireless communication systems. Once the theoretical background of CDMA and AAA has been substantiated, the thesis establishes the need for power control in mobile systems by examining simulation results. An AAA receiver with six antenna elements is proposed and evaluated in different environments as a precursor to implementation. It can be inferred that when the link is interference limited, the link capacity can be increased and it has been shown that the AAA receiver with six antenna elements increases the link capacity to about 2.9 times that of the single antenna RAKE receiver. This thesis also examines the basic concepts of VHDL and considers this as the principle means to program reconfigurable core FPGA's in the software radio. A three-layered (PC/DSP/FPGA) software radio test bed is used to implement an AAA receiver. The architecture of the test bed is designed in such a way that it can be used to evaluate the performance of various FPGA based transceivers and coding schemes etc. Many of the desirable features and flexibilities inherent in the software radio concept are available on this test bed and the system has proved to be capable of high speed digital processing and is ideally suited to the development of time critical system components. The bit error rate achieved using the implemented receiver is assessed and compared to simulation results in an environment incorporating Rayleigh fading and AWGN.