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dc.contributor.advisorPoole, K. F.
dc.contributor.advisorPeplow, Roger Charles Samuel.
dc.creatorIzzard, Martin John.
dc.date.accessioned2012-08-21T06:36:54Z
dc.date.available2012-08-21T06:36:54Z
dc.date.created1987
dc.date.issued1987
dc.identifier.urihttp://hdl.handle.net/10413/6195
dc.descriptionThesis (M.Sc.)-University of Natal, 1987.
dc.description.abstractA single chip line-rasterizer that overcomes the major bottleneck in graphics display systems has been designed by the author on a 4408 element gate array marketed by Plessey Semiconductors limited. The rasterizer was fabricated by Plessey using their 2 micron, double-level metal ISO CMOS process, in the United Kingdom. Two identifiable bottlenecks in the redraw speed on a general graphics display system are video memory bandwidth and rasterization speed (in dots produced per second). The rasterizer described here is capable of working in parallel with other rasterizers to overcome the rasterization bottleneck. Systems incorporating it are flexible and expandable. The rasterizer requests a primitive from a host or master part of the system. Once it has a primitive to work on, it begins rasterization. The rasterizer queues requests to write dots to the video memory part of the system. The device accepts two ordered pairs of 16-bit numbers as start-of-line and end-of-line coordinates, on an 8-bit bus; the dot addresses are in the form of two 16-bit numbers on a 32-bit bus. Simulation with CLASSIC showed that the device could be clocked at up to 8 MHz and would then produce dots at between 2 MHz and 4 MHz (dependent on the type of line) after the initial analysis overheads. This means that any video memory bandwidth may be fully used with this device and any improvements in memory bandwidth may be taken advantage of in a system using the parallel rasterization scheme. The Plessey test engineers exercised the device to prove the success of the fabrication. Further tests were performed by the author. In these, the rasterizer was seen to gather data correctly. The rasterization of a range of different types of lines, manhattan and general, short and long and lines of different direction, was tested. The various algorithm terminations were verified and all branches exercised. The flow control on the pixel bus was checked. The device used for all the tests, performed correctly at 10 MHz (design specification 8 MHz) which corresponds to a maximum rasterization speed of 5 MHz for 0° and 90° lines and between 2.5 MHz and 3.3 MHz for general lines. The results show that the rasterizer performance will allow full use of the memory bandwidth of the system and hence overcome the major bottleneck in many graphics display systems.en
dc.language.isoen_ZAen
dc.subjectComputer graphics.en
dc.subjectTheses--Electronic engineering.en
dc.subjectComputer-aided design.en
dc.titleA graphic rasterizer IC.en
dc.typeThesisen


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